The present invention relates generally to semiconductor processing. More particularly, the present invention relates to methods of improving conformality of oxide layers along sidewalls of deep vias in semiconductor substrates. Embodiments of the present invention may be used, for example, to form via liners with high conformality in deep and/or high aspect ratio vias.
One of the primary steps in fabricating modern semiconductor devices is forming a dielectric layer on a semiconductor substrate. As is well known in the art, such a dielectric layer can be deposited by chemical vapor deposition (CVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions take place to produce a desired film. In a conventional plasma enhanced CVD (PECVD) process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film. In general, reaction rates in thermal CVD and PECVD processes may be controlled using temperature, pressure, and/or reactant gas flow rates.
Increasingly stringent requirements for fabricating dielectric films are needed in order to produce high quality devices. Many next-generation devices use vertical or three-dimensional (3D) integration to increase device density. One challenge in vertical or 3D integration of semiconductor devices is forming conformal oxide layers along sidewalls of deep vias. These vias extend through semiconductor substrates and may have depths of 50 μm or more and openings (or critical dimensions) of 10 μm or less. The vias are subsequently filled with conductive material to provide electrical interconnects. The oxide layers provide electrical isolation between the interconnects and the semiconductor substrate. Electrical performance (e.g., dielectric breakdown, leakage, and the like) is important. A thickness of between 2000 Å to 10,000 Å along the sidewalls of the vias may be required to meet electrical requirements. Thickness uniformity is also important, both for electrical performance as well as impact on subsequent processes. For example, barrier layer and metal seed deposition processes used to form the conductive material in the vias are inherently line-of-sight processes. These processes are unable to form uniform coatings on re-entrant structures. To provide margin for the barrier layer and metal seed deposition processes, oxide layer conformality of at least 50% is generally desired.
Conventional thermal CVD and PECVD processes form dielectric layers that are thicker on horizontal or top surfaces and thinner along sidewalls and bottoms of structures such as vias. This is due at least in part to flux of reactant species during the deposition process. More reactant species reach the top surfaces than the sidewalls and bottoms of the vias. Further, a difference in deposition rate between the top surface and the sidewalls and bottoms increases with thickness of the deposited layer. This is because thickness of the deposited layer on the top surface increases at a faster rate than thickness along the bottom, increasing an aspect ratio (e.g., ratio of depth vs. width) of the via. Also, as the thickness along the top surface increases, an opening (or critical dimension) at the top of the via decreases. High aspect ratios and small critical dimensions decrease conformality (or increase non-uniformity) of deposited layers. This can lead to vias having re-entrant profiles that are difficult to fill with conductive interconnect material.
Thus, there is a need in the art for improved methods of forming conformal dielectric layers along sidewalls of vias. These and other needs are addressed throughout the present application.